Ratio logic circuits may be used to implement small area level shifters. These circuits may generally have a device that is always on, but which may be designed to be weak. This device may be a PMOS device for positive voltage level shifters. A bias voltage may generally be provided to the gate of the PMOS device to turn it on (or off); this bias voltage may typically need to be higher to keep the PMOS device weakly on when a high supply voltage is applied to the source of the PMOS device, as opposed to when a low voltage is applied to the PMOS device. One or more NMOS devices may be added to pull an intermediate node (between the PMOS and NMOS device(s)) down to near-ground voltage if an input signal is on. The NMOS device (or devices) may generally be designed to be stronger than the PMOS device so that the intermediate node may be pulled down to (near) ground when both the PMOS and NMOS devices are both on. The voltage at the intermediate node may then be inverted to create an output signal.
Such ratio logic level shifters may often be connected such that a device may provide an input signal, and the output signal may be a voltage-shifted version of the input signal. One possible use of such level shifting is for testing purposes. For example, it may be desirable to sweep a level shifter output voltage across a device under test, which may be connected to the level shifter output, in order to measure certain characteristics of the device under test. In conjunction with the sweeping of the voltage, the bias voltage supplied to the PMOS device may need to be changed in accordance with the varying voltage level, to ensure proper functioning of the level shifter. Having to switch the bias voltage during the course of such testing may cause a delay in the testing process. This problem may be particularly acute in cases where there are many devices to be tested and/or where many tests are required.